G06F9/3016- Decoding the operand specifier, e.g.G06F9/22- Microcontrol or microprogram arrangements.G06F13/00- Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units.G06F12/0875- Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g.G06F12/084- Multiuser, multiprocessor or multiprocessing cache systems with a shared cache.G06F12/0806- Multiuser, multiprocessor or multiprocessing cache systems.G06F12/0802- Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g.G06F12/08- Addressing or allocation Relocation in hierarchically structured memory systems, e.g.G06F12/02- Addressing or allocation Relocation.G06F12/00- Accessing, addressing or allocating within memory systems or architectures.G06F9/30181- Instruction operation extension or modification.dynamic instruction scheduling, out of order instruction execution of compound instructions dynamic instruction scheduling, out of order instruction execution G06F9/38- Concurrent instruction execution, e.g.G06F9/30- Arrangements for executing machine instructions, e.g.using an internal store of processing equipment to receive or retain programs control units using stored programs, i.e. G06F9/06- Arrangements for program control, e.g.G06F9/00- Arrangements for program control, e.g.G06- COMPUTING CALCULATING OR COUNTING.239000003795 chemical substances by application Substances 0.000 description 1.238000004519 manufacturing process Methods 0.000 description 2.230000004927 fusion Effects 0.000 title claims abstract description 22.Application filed by Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi filed Critical Ido Ouziel Priority to US15/143,522 priority Critical patent/US20160246600A1/en Priority to US15/143,520 priority patent/US10649783B2/en Publication of US20170003965A1 publication Critical patent/US20170003965A1/en Application granted granted Critical Publication of US10649783B2 publication Critical patent/US10649783B2/en Status Active legal-status Critical Current Adjusted expiration legal-status Critical Links Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Family has litigation First worldwide family litigation filed litigation Critical (A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License. ( en Inventor Ido Ouziel Lihu Rappoport Robert Valentine Ron Gabor Pankaj Raghuvanshi Original Assignee Ido Ouziel Lihu Rappoport Robert Valentine Ron Gabor Pankaj Raghuvanshi Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number US15/143,520 Other versions US10649783B2 Google Patents Efficient instruction fusion by fusing instructions that fall within a counter-tracked amount of cycles apartĭownload PDF Info Publication number US20170003965A1 US20170003965A1 US15/143,520 US201615143520A US2017003965A1 US 20170003965 A1 US20170003965 A1 US 20170003965A1 US 201615143520 A US201615143520 A US 201615143520A US 2017003965 A1 US2017003965 A1 US 2017003965A1 Authority US United States Prior art keywords instruction instructions fusible processors cache Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US20170003965A1 - Efficient instruction fusion by fusing instructions that fall within a counter-tracked amount of cycles apart US20170003965A1 - Efficient instruction fusion by fusing instructions that fall within a counter-tracked amount of cycles apart
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